N3E is only 1.6x denser than N5 and that only apply to logic transistors. TSMC assumes logic makes up 50% of a hypothetical chip to arrive at 1.3x scaling. It wouldn’t come anywhere near close to actually doubling in real chips.
Analog and SRAM scaling has been decelerating for years. TSMC N3E has the same SRAM cell size as N5. Samsung 4nm has the same SRAM cell size as 7nm. Because they don’t scale with logic, every succeeding generation these components will take up more and more of the silicon hence AMD’s move to chiplets.
To some extent, SRAM scaling isn’t that limiting of a factor anymore. Current design practices call for tons of dark silicon and highly specialized elements, and the effective density of newer chips is still increasing rather rapidly.
A10 - 16nm TSMC - 3.28B/125mm2
A11 - 10nm TSMC - 4.3B/87mm2
A12 - 7nm TSMC - 6.9B/83mm2
A13 - 7nm TSMC - 8.5B/98mm2
A14 - 5nm TSMC - 11.8B/88m2
A15 - 5nm TSMC - 15B/107mm2
When they don’t get a node shrink, they just blow up the area to get similar transistor count scaling. Is the pace a doubling every 2 years? Not quite, but the effective pace is rather close.
Yes, there will be progress but that’s not really what Moore’s Law is about. Moore’s Law is not an observation that there will be progress eventually but an observation at specific rate of that progress. It’s not “transistors will double eventually”, or “transistors will increase somewhat every 2 years”.
With exponential growth, the tiniest decrease compounds to a major difference. 2 to the power of 3 is 8; the A16 has 16B transistors not 26B. That’s with the gains of the last DUV nodes, 16->10->7nm. EUV to EUV, 5nm to 3nm doesn’t match up to that. It seems transistor growth with EUV nodes is becoming linear so not really in line with the exponential growth of Moore’s Law.
The chips could be larger but flagship phones would have to become even more expensive, and physically larger to dissipate the extra heat. Dennard Scaling mattered more in practice than Moore’s Law ever did but that ended over a decade ago. At the end of the day, all the microarchitecture and foundry advances are there to deliver better performance for every succeeding generation and the rate of that is definitely decelerating.
In 3 years, the only Android chip that has a perceivable difference in performance from the Kirin 9000 is the 8 Gen 2, which cost $160 just for the chip. That performance difference isn’t even enough to be a selling point; the Mate 60 Pro is in the same price range as those 8 Gen 2 phones yet is still perfectly competitive in that market segment.
Technically, Moore’s Law relates to the cost curve for any given complexity, not necessarily the transistor count. That is, that the most efficient point of marginal cost/marginal performance approximately doubles every two years (implicitly, as the node shrinks).
The concern people have is that each node shrink isn’t delivering the same benefits as before… But is that true, or is the node-to-node cadence just rising? I pose that the shrinking cadence is simply a problem of lack of funding to the big fabs, not one of the technology becoming intrinsically infeasible.
In particular, I’d like to point out that the switch from planar to FinFET was also largely driven by the planar technology becoming rather infeasible for scaling at that time - we should see a similar transition to GAAFET soon and I’m tentatively hopeful for TSMC’s future GAAFET node densities after they ship N2 (which, itself, is barely a node shrink so much as it is a technology demonstrator).
Unless China can co-develop the EUV machine with the node itself, they will be very very late to this gap in foundry capability. If they can, they will only be very late.
Transistor density isn’t doubling every 2 years.
N3E is only 1.6x denser than N5 and that only apply to logic transistors. TSMC assumes logic makes up 50% of a hypothetical chip to arrive at 1.3x scaling. It wouldn’t come anywhere near close to actually doubling in real chips.
Analog and SRAM scaling has been decelerating for years. TSMC N3E has the same SRAM cell size as N5. Samsung 4nm has the same SRAM cell size as 7nm. Because they don’t scale with logic, every succeeding generation these components will take up more and more of the silicon hence AMD’s move to chiplets.
To some extent, SRAM scaling isn’t that limiting of a factor anymore. Current design practices call for tons of dark silicon and highly specialized elements, and the effective density of newer chips is still increasing rather rapidly.
A10 - 16nm TSMC - 3.28B/125mm2
A11 - 10nm TSMC - 4.3B/87mm2
A12 - 7nm TSMC - 6.9B/83mm2
A13 - 7nm TSMC - 8.5B/98mm2
A14 - 5nm TSMC - 11.8B/88m2
A15 - 5nm TSMC - 15B/107mm2
When they don’t get a node shrink, they just blow up the area to get similar transistor count scaling. Is the pace a doubling every 2 years? Not quite, but the effective pace is rather close.
Yes, there will be progress but that’s not really what Moore’s Law is about. Moore’s Law is not an observation that there will be progress eventually but an observation at specific rate of that progress. It’s not “transistors will double eventually”, or “transistors will increase somewhat every 2 years”.
With exponential growth, the tiniest decrease compounds to a major difference. 2 to the power of 3 is 8; the A16 has 16B transistors not 26B. That’s with the gains of the last DUV nodes, 16->10->7nm. EUV to EUV, 5nm to 3nm doesn’t match up to that. It seems transistor growth with EUV nodes is becoming linear so not really in line with the exponential growth of Moore’s Law.
The chips could be larger but flagship phones would have to become even more expensive, and physically larger to dissipate the extra heat. Dennard Scaling mattered more in practice than Moore’s Law ever did but that ended over a decade ago. At the end of the day, all the microarchitecture and foundry advances are there to deliver better performance for every succeeding generation and the rate of that is definitely decelerating.
In 3 years, the only Android chip that has a perceivable difference in performance from the Kirin 9000 is the 8 Gen 2, which cost $160 just for the chip. That performance difference isn’t even enough to be a selling point; the Mate 60 Pro is in the same price range as those 8 Gen 2 phones yet is still perfectly competitive in that market segment.
Technically, Moore’s Law relates to the cost curve for any given complexity, not necessarily the transistor count. That is, that the most efficient point of marginal cost/marginal performance approximately doubles every two years (implicitly, as the node shrinks).
The concern people have is that each node shrink isn’t delivering the same benefits as before… But is that true, or is the node-to-node cadence just rising? I pose that the shrinking cadence is simply a problem of lack of funding to the big fabs, not one of the technology becoming intrinsically infeasible.
In particular, I’d like to point out that the switch from planar to FinFET was also largely driven by the planar technology becoming rather infeasible for scaling at that time - we should see a similar transition to GAAFET soon and I’m tentatively hopeful for TSMC’s future GAAFET node densities after they ship N2 (which, itself, is barely a node shrink so much as it is a technology demonstrator).
Unless China can co-develop the EUV machine with the node itself, they will be very very late to this gap in foundry capability. If they can, they will only be very late.